1. Field of the Invention
The present invention relates to a semiconductor device, and, particularly, to a method of manufacturing a semiconductor device having a multilayered wiring structure.
2. Description of the Related Art
Configuration of Semiconductor Device Comprised of Multilayered Wiring
In a semiconductor device having a multilayered wiring layer in which Al—Cu wirings added with Cu in Al to suppress failures caused by electromigration are laminated, a connecting portion between two wiring layers generally has such a configuration as shown in FIG. 2, for example.
FIG. 2 is a typical cross-sectional view showing one example of a partial structure of a semiconductor device having a structure wherein wiring layers are laminated. Described specifically, the present figure illustrates two wiring layers insulated and isolated from each other by an interlayer insulating layer, and an electrically-connected portion between these two wiring layers.
In FIG. 2, reference numeral 120 indicates a first wiring layer (Al—Cu wiring), reference numeral 200 indicates an interlayer wiring, reference numeral 320 indicates a second wiring layer (Al—Cu wiring), reference numerals 110, 130, 310 and 330 indicate cap layers, and reference numerals 400, 401 and 402 indicate interlayer insulating layers, respectively. An upper surface (as viewed in the direction opposite to arrow S) of the first wiring layer 120 in the neighborhood of an end thereof, and the interlayer wiring 200 are electrically connected each other with the cap layer 130 interposed therebetween. A lower surface (corresponding to a surface as viewed in the direction indicated by arrow S) of the second wiring layer 320 in the neighborhood of an end thereof, and the interlayer wiring 200 are electrically connected to each other with the cap layer 310 interposed therebetween.
The first wiring layer 120 is electrically connected to an unillustrated interlayer wiring with the cap layer 110 provided on its lower surface interposed therebetween. The second wiring layer 220 is electrically connected to an unillustrated interlayer wiring with the cap layer 330 provided on its upper surface interposed therebetween.
The cap layers 110, 130, 310 and 330 provided in contact with the first wiring layer 120 and the second wiring layer 320 are respectively ones formed by laminating films with at least TiN as a principal component.
In order to insulate the first wiring layer 120, the second wiring layer 320 and other wiring layers (not shown), the interlayer insulating layers 400, 401 and 402 are respectively provided among the first wiring layer 120, the second wiring layer 320 and other wiring layers (not shown).
The interlayer wiring 200 for connecting the first wiring layer 120 and the second wiring layer 320 is made up of an adhesive layer 210 and a W film 220. The adhesive layer 210 is provided so as to surround a lower surface and side surfaces (surfaces parallel to an axial direction thereof indicated by arrow S) of the W film 220.
Incidentally, the arrow S in FIG. 2 indicates the substrate side, and the direction parallel to the arrow S in FIG. 2 means the direction normal to the surface of a substrate. In FIG. 2 and the drawings described subsequently to FIG. 2, the surface (direction) on the substrate side might be abbreviated as a lower surface (lower side), and the surface (direction) opposite to it might be abbreviated as an upper surface (upper side) for convenience of explanation.
Such a connecting structure between the wiring layers as shown in FIG. 2 is included in the semiconductor device in large numbers. There might be cases in which the rate of occurrence of failures caused by electromigration much varies every individual connecting portions. In this case, a problem takes place in reliability upon design of the semiconductor device if the density of a current caused to flow in each wiring layer is set with each connecting portion hard to develop or cause a failure as the reference. Therefore, a problem arises in that the density of a current caused to flow in each wiring with each connecting portion easy to cause a failure as the reference must be set low.